Design of a 12-bit cyclic RSD ADC sensor interface IC using the intelligent analog IP library

Within this paper we present an Intelligent Analog IP design flow and its successful application on an industrial-level mixed-signal ASIC design. This novel design flow is based on a library of flexible (configurable), robust (Design for reliability awareness) and technology-independent Analog IPs, available from primitive device level up to complex circuit blocks. Its application leads to a significant increase in efficiency of the overall design process due to reduced design and layout cost, speed-up or even avoidance of redesign cycles and very fast technology porting. For the design of a multi-physical SMART sensor interface with a low-power 12-bit RSD ADC we already saved 43 % of layout time using the Intelligent Analog IP design flow. In addition, system-level and schematic design as well as post-layout verification was more efficient compared to conventional design flows.