Power grid analysis of CMOS devices for EMI prediction

In this paper a methodology for the analysis of the dynamic supply current of digital CMOS devices is described. Especially the impact of parasitic inductance of supply lines will be investigated. Normally the dynamic current will be transmitted as conducted emission via the package to the PCB level. Together with the parasitic inductance of package and PCB traces this leads to a bounce of the IC ground level. Connected signal lines act as antennae and thus lead to radiated emission. Consequently the methodology is suitable to predict the EMI behavior of the analyzed IC. For the described di/dt-analysis the switching gates as noises sources as well as the supply lines as coupling paths will be taken into account. One major problem for performing an analysis of VLSI ICs is the complexity. This can be handled by simplifying the gate models and by analyzing only selected nets of interest.