Technology options and their influence on routing for interposer-based memory processor integration

Further improvements in system performance are often limited by the achievable bandwidth between processor and memory. 3D integration attracts more and more glob-al players and a multitude of technological options are available to realize high-performance systems. Currently, mainly stacked solutions are considered due to their at-tractive compactness. But designing in a thermally balanced way is very challenging and often ends up in ex-pensive cooling concepts. An alternative is the interposer-based side-by-side arrangement of the systems. In this technology feature we discuss different options (e.g. technology, arrangement) for memory/processor-integration. For silicon interposers two different options for the dielectric material are currently favored; namely SiO2 and polymers. Both materials necessitate their own integration schema. For example SiO2 processing re-quires expensive planarization steps (e.g., CMP - chemical mechanical polishing). Polymer based surfaces don't re-quire such steps. But because advanced lithography steps require flat surfaces, the achievable resolution of line/space features is low. We compare the presented technology options in the system level context with the interconnections between a memory and a processor. For this comparison we consider the overall costs and the achievable data rate of the processor/memory interface.