Crack and damage evaluation in low-k BEoL stacks under assembly and CPI aspects

Miniaturization and increasing functional integration as the electronic industry drives push the development of feature sizes down to the nanometer range. Moreover, harsh operational conditions and new porous or nano-particle filled materials introduced on both chip and package level - low-k and ultra low-k materials in Back-end of line (BEoL) layers of advanced CMOS technologies, in particular - cause new challenges for reliability analysis and prediction. The authors show a combined numerical/experimental approach and results towards optimized fracture and fatigue resistance of those BEoL structures under manufacturing/packaging as well as chip package interaction (CPI) aspects by making use of bulk and interface fracture concepts, in multi-scale and multi-failure modeling approaches with several kinds of failure/fatigue phenomena. In addition, manufacturing induced residual stresses in the Back-end layer stack have an essential impact on damage behavior, because they superpose functional and CPI loads. Their determination with a spatial resolution necessary for typical BEoL structure sizes is a critical issue. The nano-scale stress relief technique (fibDAC) makes use of tiny trenches placed with a focused ion beam (FIB) equipment at the position of stress measurement. Digital image correlation algorithms applied to SEM micrographs captured before and after ion milling allows to conclude on stresses released. Residual stresses can be computed with the help of appropriate, adjusted FEA models.