Elastic anisotropy of Cu and its impact on stress management for 3D IC

This article presents a study on elastic anisotropy of Cu by indentations at different penetration depth ranges (sub-10 nm, several-10 nm, and several-100 nm), and the impact of elastic anisotropy on the stress in 3D stacked integrated circuits (3D ICs). The reduced modulus, E-R, values determined at sub-10 nm indentations on Cu single crystals are very close to the unidirectional values. Similarly, cross-sectional sub-10 nm indentation tests on the Cu grains in a through-silicon via (TSV) show unidirectional E-R values. In contrast, the Hill's average values are observed at several-100 nm indentations. We propose that before lattice rotation happens within a volume beneath the indentation, elastic anisotropy can be strongly reflected in the E-R value. When the experimentally measured Cu elastic anisotropy is used in a technology computer-aided design simulation of a Cu-filled TSV, significant impacts are observed on the stress field and the carrier mobility variation in an active Si region.