System simulation with PULP virtual platform and SystemC

Driven by performance, power and energy requirements compute platforms evolved from single-core homogeneous into highly parallel heterogeneous architectures. These architectures use different CPUs, GPUs, accelerators, interconnects, memories, etc., and target diverse applications creating avast design space. Moreover, ever-growing security concerns leverage the adoption of open source silicon designs and tools, specially those with collaborative research and engineering efforts from industry and academia to develop and maintain for the long term. In this context, RISC-V based solutions are an outstanding choice and virtual platforms are essential for a fast design cycle. However, simulation frameworks often do not provide off-the-shelf interoperability hindering the reusability of existing models. In this paper, we present for the first time a coupling of the PULP virtual platform, which provides manycore RISC-V accelerators in a feature-rich simulation environment, with SystemC/TLM-2.0, a de facto standard in industry that is also largely used in the academia. Furthermore, we evaluate the coupling of simulation engines and demonstrate its usefulness in a case study.