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  4. A high speed asynchronous multi input pipeline for compaction and transfer of parallel SIMD data
 
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2018
Conference Paper
Title

A high speed asynchronous multi input pipeline for compaction and transfer of parallel SIMD data

Abstract
Image sensors with programmable, highly parallel signal processing, so called Vision-Systems-on-Chip, perform computationally intensive tasks directly on the sensor itself. Therefore it is possible to limit the amount of output data to relevant image features only. Reading out such features presents a major challenge, since the position and number of features often is not known. Conventional synchronous buses as well as special event-based readout paths are unsuitable for such a system, since both continuous data, e.g. complete images, and sparse data, like feature coordinates, have to be transfered. A readout path based on an asynchronous pipeline is presented, which supports both readout modes with high speed. Furthermore, a method is introduced that, by serialization, allows for arbitrary data word widths without storing any control information within the data stream. The developed circuit components were measured on a proof-of-concept test chip in a 180 nm CMOS technology and were compared with implementations of asynchronous pipelines found in literature. In addition, the use of the pipeline in a Vision-System-on-Chip, which is still in production, is demonstrated.
Author(s)
Hoppe, Christoph  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Döge, Jens  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Reichel, Peter  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Russell, Patrick
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Reichel, Andreas  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Schneider, Peter  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Mainwork
24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018  
Project(s)
cSoC3D
Funder
Bundesministerium für Bildung und Forschung BMBF (Deutschland)  
Conference
International Symposium on Asynchronous Circuits and Systems (ASYNC) 2018  
Open Access
File(s)
Download (633.01 KB)
Rights
Use according to copyright law
DOI
10.24406/publica-r-400738
10.1109/ASYNC.2018.00027
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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