Defect Detection of Solder Connection Layer in Power Electronic Components by Laser Speckle Photometry

Reliability and quality of power electronic components are critical factors which should be taken into considerations before the packaging process. During chip application on ceramic-based substrates, defects can occur in the soldered or sintered connection layer. These defects will result in a reduction in heat dissipation, which can lead to overheating of the chip component and thus to a reduction in its service life. In addition, the connection layer is subjected to mechanical stresses caused by the thermal mismatch of the chip component and the base substrate. In this case, the imperfections of the layer will reduce the mechanical integrity. Therefore, the detection of defects in the connection layer between chip and substrates is particularly important during the manufacturing process of high-performance power electronics to guarantee a good quality. The laser speckles are generated when an optical rough surface is illuminated by a coherent light source. The scattered waves from various points of the illuminated surface interfere in the observation plane, producing the speckle pattern - a spatial structure with randomly distributed intensity minima and maxima. The speckle pattern can be regarded as the fingerprint containing the 3D information of sample surface. Time-resolved Laser Speckle Photometry (LSP) is an inline optical method based on the evaluation of the temporal change of speckle patterns. In this method, an optically rough surface is illuminated by a laser beam creating the speckle patterns. A short thermal excitation leads to the deformation of the surface, which generates time-varied speckles. These are recorded by a digital camera for the further evaluations. A developed concept for quality monitoring of power electronic components, especially the defect detection in the solder connection layer based on the LSP will be presented in current paper. The LSP implementation will be carried out using the example of solder layer with pre-defined defect patterns between chip and ceramic substrate. The defect with a 20 % bulk volume of the connection layer can be detected in the preliminary experiments, which shows a great potential for the development of the LSP to inspect the connection quality of chips during the manufacturing of power electronics.