Multi-scale simulation methodology for stress assessment in 3D IC

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D integrated circuit (IC) technologies are outlined. A set of physics-based compact models for a multi-scale simulation, to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D through-silicon-via (TSV) technology, is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far.