Analyzing the switching behavior of ESD-protection transistors by very fast transmission line pulsing

This work describes, how the very fast transmission line pulsing (VFTLP)-technique can be used to characterize the switching behavior of ESD protection elements. In a first application we investigate the behavior of a protection element consisting of a lateral and vertical transistor part. This element shows a good ESD performance under 100 ns-TLP and HBM conditions. Under CDM relevant conditions, however, we could identify by means of VFTLP a delayed triggering of the vertical transistor part, which leads to an increased maximum voltage and thus to a low-failure threshold. In the second application we propose a methodology for the extraction of the base transit time parameter which improves the accuracy of a compact transistor model during turn on.