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  4. A 1 megapixel HDR image sensor SoC with highly parallel mixed-signal processing
 
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2015
Conference Paper
Title

A 1 megapixel HDR image sensor SoC with highly parallel mixed-signal processing

Abstract
This work aims to develop a universal and flexibly programmable image sensor SoC for a variety of industrial image acquisition and processing applications. It is comprised of an array of 1024x1024 pixel cells with a pitch of 8.75mm and features linear/logarithmic characteristics. In logarithmic mode, dynamic range exceeds120 dB. The fully programmable, column-parallel, mixed-signal data path from charge-based pixel readout and analogue processing via multi-slope analogue-to-digital conversion to the full custom digital 8-bit ALU allows for data processing with more than 100 GOps.
Author(s)
Döge, Jens  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Hoppe, Christoph  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Reichel, Peter  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Peter, Nico  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Mainwork
International Image Sensor Workshop, IISW 2015. Papers. Online resource  
Project(s)
Enlight
Funder
Bundesministerium für Bildung und Forschung  
Conference
International Image Sensor Workshop (IISW) 2015  
Link
Link
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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