Analog frontend for ultra low power 60-GHz RFID tag for back-scattering communication

An analog frontend for 60-Ghz passive RFID tag is presented. It is designed in CMOS SOI process on the 7 Ohm*cm substrate. A new rectifier concept for RF to DC conversion is presented. It utilizes the regular CMOS topology, anyway a dynamic gate biasing is used for achieving a better sensitivity and efficiency for -5 to -1 dBm input power range. Also bulk back-biasing is used for transistor threshold voltage modulation. With 10 KOhm equivalent load the rectifier produces 100 mV at -11.4 dBm and 400 mV at -3.5 dBm input power. The entire analog frontend produces 400 mV output voltage already at -1 dBm input power with 10 KOhm loading. The modulator is designed to absorb only 24% of the input power in the passive mode, while providing 4 dB change in the reflection coefficient. The demodulator is sized so that it takes another 14% of the input power, which is still sufficient to demodulate the amplitude modulated signal from the reader side. To ensure the RFID tag low power operation the tag components are designed to work at 400 mV supply from the rectifier, with up to 100mV voltage drops during the communication.