Low cost wafer-level 3-D integration without TSV

Most of the wafer level 3-D technologies are using Through-Silicon Vias (TSV). The main barriers for these approaches are high cost, issues with electrical isolation within the Si via and the need of high investments for new equipment which is not used in WLP up to now. A planar integration technology of ultra-thin bare dice in a Wafer-Level Thin Film technology yield to a high-dense module will be presented here. This Thin Chip Integration (TCI) technology consists of one or more ultra-thin chips which are stacked on a larger sized standard thick chip and which are interconnected by a thin film routing. The wafer level thinning of the ICs to 20 - 40 mu m leads to the integration of IC into a redistribution. The ICs are bonded on a carrier chip on wafer-level using Photo-BCB (Cyclotene 4000 from The Dow Chemical Company). A standard thin film multilayer which was developed for a redistribution process is realized in a planar fashion on top of the embedded system. The metallization is based on a Ti:W / Cu tie layer, which is subsequently electroplated. Photo-BCB is used as interlevel low k dielectric. The final metallization opens the possibility to stack a FC on top of the embedded chips. The final module consists of an embedded IC on a CMOS or sensor wafer with a third IC FC-bonded on top. An example of this approach is presented in details including electrical and reliability tests. All steps are done on wafer level enabling a low cost technology which can be manufactured using standard redistribution infrastructure already established in the packaging industry. This unique module concept can lead to new applications that would be not feasible before. It will lead the packaging world to new low cost 3-D packages.