Integrated Foreground Calibration for a High Speed Time Interleaved SAR Converter

A multi-stage, integrated, foreground self-calibration for a time interleaved, buffer in the loop SAR converter is proposed. This ADC topology integrates the input buffer and the current DAC imposes no distortions on the references for optimum system-on-chip integration. No analog elements are inserted in the SAR loop to maintain the maximum speed. The algorithm uses only basic calculations, which enables the integration in mature CMOS processes with small gate count. The approach is calibrating the comparator offset, the nonlinearities in the DACs and the gain and offset of a complete time interleaving structure. The proposed method is verified in an exhaustively simulated 180nm design for an 300MS/s 10bit ADC.