Development of a Test Vehicle for the Accurate Measurement of Seed Layer Contact Resistance in 2.0 μm-diameter Vias for High-density Interconnects Wafer-level Packaging

In the increasingly sophisticated semiconductor packaging landscape, multiple dies can be connected side-by-side on an interposer or stacked vertically to achieve shorter distances and higher interconnects density. These technologies allow the Heterogeneous Integration of chiplets with increased functionality, higher speed and better power efficiency. The high interconnects density and the concomitant shrinkage of the critical dimensions (e.g. RDL width/pitch and diameters of the vertical interconnections), increase exponentially the importance of the contact resistance between metal interfaces. In wafer-level packaging, interconnects are commonly manufactured by sputter deposition of a seed layer followed by Cu electroplating. The main challenge, prior PVD, is the elimination of the native oxide present on the exposed metal contacts, coupled with the presence of organic load released by the polymer dielectrics widely used in WLP (e.g. PI and PBO) that contaminates the process chambers of the PVD platform.This work presents an improved wafer-level manufacturing process for fabricating Kelvin resistors based on Al/Ti/Cu metallization and via diameter ranging from 2.0 μm up to 20.0 μm. Experimental Rc data have shown that the sensitivity of the fabricated structures, in regard of the chamber conditions, is inversely proportional to the contact area. A test run of 25 wafers processed at a throughput of 55 wafers/hour on the Indexer PVD platform has revealed a constant Rc on 10.0 and 20.0 μm via structures, but instead a significant excursion on the smaller vias. For example, 2.0 μm via structures exhibited Rc = 36.5 mΩ on wafer#1 and Rc = 44 mΩ on wafer#25. This corresponds to a 20% increase within lot. In conclusion, the fabricated Kelvin resistors are very suitable test vehicles to be used for benchmarking PVD seed layer processes and to establish optimum conditions ensuring high yield and a constant wafer-to-wafer quality in next-generation high-density interconnects WLP applications.