Low-cost Chip2Chip integration for partitioning processing and memory

This paper presents a novel chip-to-chip packaging approach. Most electronic systems comprise a processing unit and some memory as basis components. Devices with a high compute power also demand a lot of embedded memory. In many cases this embedded memory is integrated within the same IC. This is maybe not the best solution for each case, since processing unit and embedded memory have different requirements. So a technology could be optimized for performance or memory but not both. Also the demand for metal stack is distinct. Processing units need a lot of metal layers for proper routing and memory typically comes out with a lot less, because of the regular arrangement. Because of these differences it can be suitable to divide processing and memory during production and merge both during assembly. In this paper the idea to partitioning processing and memory is presented and an example low-cost chip stack-up will be described, that is currently in production.