Survey on electrostatic susceptibility of integrated circuits

From traditional assumptions and simplifications, different attitudes towards electrostatic discharges (ESD) in present microelectronics have been developed. The central question remains, which level of ESD-susceptibility and which level of costly external protection measures is needed to limit yield losses and potential reliability risks for integrated circuits. This paper addresses influences, links and current trends in protection design and ESD-test in the context of ESDsusceptibility of integrated circuits. One focus will be the Charged Device Model (CDM).