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  4. Automatic DRAM Subsystem Configuration with irace
 
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2023
Conference Paper
Title

Automatic DRAM Subsystem Configuration with irace

Abstract
Nowadays, DRAM subsystem configuration includes a large number of parameters, resulting in an extensive design space. Setting these parameters is a challenging step in system design as the parameter-workload interactions are complex. Since design space exploration by exhaustive simulation is infeasible due to limited computing resources and development time, semi-automatic configuration involving both manual as well as simulation-based decisions is state-of-the-art. However, it requires a lot of expertise in the DRAM domain as well as application knowledge, and there is no guarantee for a good performance of the resulting subsystem. In this paper, we present a new framework that fully automatizes the DRAM subsystem configuration for a given parameter space and set of target applications. It is based on irace, a software package originally developed for automatic configuration of optimization algorithms. We show that the framework finds nearly-optimal configurations, while only a fraction of all application-configuration combinations has to be evaluated. In addition, all returned configurations perform better than a predefined standard configuration. Thus, our framework enables designers to automatically determine a suitable DRAM subsystem for their platform.
Author(s)
Steiner, Lukas
Delazeri, Gustavo
Prando da Silva, Iron
Fraunhofer-Institut für Experimentelles Software Engineering IESE  
Jung, Matthias
Fraunhofer-Institut für Experimentelles Software Engineering IESE  
Wehn, Norbert
Mainwork
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, RAPIDO 2023  
Project(s)
Mannheim-Memtonomy  
Funder
Bundesministerium für Bildung und Forschung  
Conference
Conference "Rapid Simulation and Performance Evaluation: Methods and Tools" 2023  
DOI
10.1145/3579170.3579259
Language
English
Fraunhofer-Institut für Experimentelles Software Engineering IESE  
Keyword(s)
  • Automatic Algorithm Configuration

  • Design Space Exploration

  • DRAM

  • irace

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