High Density Interconnect Processes for Panel Level Packaging

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Package (3D SIP) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for 3D SIPs with chips embedded into an organic laminate matrix. At first 6x6 mm 2 chips with Cu bumps (100 mm pitch) are placed into holes of a PCB core layer with low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the small gap down to 15 mm between chips and core. The core provides fiducials for a local alignment of following processes, limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305x256 mm 2 panel format, aiming for a final size of 600x600 mm 2 . On the top side of embedded chips a 25 mm dielectric film is applied and the bump surface is exposed by plasma etching. By sputtering and electroplating of Cu contacts to the chips are formed without via opening. High aspect ratio vias around the chip to lower interconnect layers are formed by UV laser drilling. At via diameters of 17 mm a drill hole depth of 74 mm was achieved (aspect ration 4.4:1). Currently a microvia filling by Cu plating using a newly developed electrolyte could be demonstrated for aspect ratios up to 2.5:1. Then in a 7 mm dry film photo resist forming of 4 mm RDL structures was demonstrated by a newly developed Laser Direct Imaging (LDI) machine.