Path-based statistical gate-level analyses considering timing and energy

Global and local fluctuations in leading-edge semiconductor manufacturing affect today's integrated circuits. While the former had been known and counteracted for years already, the latter arose when moving device dimensions into the deep submicron regime. In industrial digital circuit design, global and local variations are considered separately by process corners and on-chip variations. Both approaches have been criticized being inaccurate. As an alternative, for instance Statistical Static Timing Analysis applies analytical standard cell models to handle variability on gate level. We think, however, that multivariate statistical models may be an attractive solution as well since they may combine information on timing and power. In this paper, we propose a fully statistical approach for standard cell modelling and its application in statistical gate-level analyses combining propagation delay and energy consumption for timing paths. Using 45-nm predictive technology models, our gate-level results are close to SPICE reference simulations. Nevertheless, further research on statistical standard cell modeling is required on the way towards statistical analyses of complete digital blocks.