A reliable supervisor system utilizing an FD-SOI FPGA and MRAM for COTS-based payload data processing

This paper presents a supervisor system for a Data Processing Unit (DPU) designed for imaging payloads in small satellites. The supervisory system is powered by the Certus NX FD-SOI FPGA and runs on the Zephyr RTOS, utilizing a soft-core RISC-V processor along with reliable MRAM for firmware and configuration storage. The supervisor manages latch-up protection, power monitoring, and redundancy management. Both the gateware and software stacks are predominantly based on open-source tools. The DPU with has successfully passed thermal and vibrational qualification, with a flight model scheduled for launch aboard an Earth observation microsatellite in 2026.