Algorithm for the Automatic Verification of Complex Mixed-Signal ICs regarding ESD-Stress

In this publication, an algorithm is described which automates the verification of a com¬p¬lex integrated circuit (IC) with regard to the behavior under transient high voltage impulses (e.g. ESD). Here, the complexity of the whole circuit diagram is being reduced in a first step in order to carry out a transient simulation with high current simulation models time-efficiently in a second step. The nowadays usual manual extraction of the relevant circuit parts for such a transient analysis is then automated and therefore, the error susceptibility of this process is minimized as well. The algorithm is embedded in a commercial design frame¬work for IC-design and uses the data structures already existing.