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  4. Algorithm for the Automatic Verification of Complex Mixed-Signal ICs regarding ESD-Stress
 
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2005
Conference Paper
Titel

Algorithm for the Automatic Verification of Complex Mixed-Signal ICs regarding ESD-Stress

Alternative
Algorithmus zur automatischen Verifikation komplexer Mixed-Signal ICs gegenüber ESD-Belastungen
Abstract
In this publication, an algorithm is described which automates the verification of a com¬p¬lex integrated circuit (IC) with regard to the behavior under transient high voltage impulses (e.g. ESD). Here, the complexity of the whole circuit diagram is being reduced in a first step in order to carry out a transient simulation with high current simulation models time-efficiently in a second step. The nowadays usual manual extraction of the relevant circuit parts for such a transient analysis is then automated and therefore, the error susceptibility of this process is minimized as well. The algorithm is embedded in a commercial design frame¬work for IC-design and uses the data structures already existing.
Author(s)
Morgenstern, H.
Groos, G.
Köhne, H.
Reichl, H.
Hauptwerk
2005 PhD research in microelectronics and electronics. PRIME, proceedings of the conference. Vol.2
Konferenz
Conference PhD Research in Microelectronics and Electronics (PRIME) 2005
Thumbnail Image
DOI
10.1109/RME.2005.1543042
Language
German
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Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM
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