Analyzing the Influence of RDL Stack-up on Wafer Warpage in FOWLP through Experimental and Numerical Investigations

Fan-out Wafer Level Packaging (FOWLP) is considered as a technology that enables new packaging options in heterogeneous integration and therefore is an important trend in microelectronics.Within the RDL-first approach of the FOWLP technology, the redistribution layers (RDL) are realized on a wafer level process before chips and encapsulation are applied. To enable high precision interconnects, a major challenge is to control the warpage of the wafer. Here, a precise numerical simulation is necessary to assess and predict the influence of different designs and materials.This paper concentrates on the determination of the warpage during the first layers of multiple RDL process steps. In a first step a simple bilayer sample is analyzed and simulated to achieve a consistent modelling approach of the RDLs polyimide (PI). With that successfully accomplished, a build-up with three RDL is simulated and compared with in-process warpage measurements. The complex RDL layout, which leads to a mixture of copper (Cu) and PI with different proportions needs to be considered in such an approach. For simplification a homogenization approach was chosen and extended to facilitate the numerical model. The results are discussed in comparison of modelling and experimental results. To improve the precision of the approach a new concept of considering viscoelastic behavior of the PI is being introduced, because neglecting the effect can cause errors in the range of 80%. With this result it is shown, that the impact of RDL design can be evaluated in a warpage simulation for a three layer RDL.