Challenges and advantages of cut solar cells for shingling and half-cell modules

Cutting silicon solar cells from their host wafer into smaller cells reduces the output current per cut cell and therefore allows for reduced ohmic losses in series interconnection at module level. This comes with a trade-off of unpassivated cutting edges, which result in power losses. This performance drop can be seen in fill factor FF and open-circuit voltage V<inf>OC</inf> losses on cut cell level. Based on experimental realization of different solar cell layouts on the same industrial blue wafers (solar cell precursors), a combined simulation method to predict the performance on module level is demonstrated. This method uses Gridmaster+ for cell simulation and SmartCalc. Module for module simulation. The accuracy of the simulations is demonstrated by comparing with experimental results both from host and cut cell level. In addition, significant influence of the current–voltage (I–V) measurement configuration is demonstrated, mainly affecting FF. Using flexible methods like GridTOUCH^® for I–V testing gives fast results but can also lead to overestimation of the host cell performance, resulting in overestimated cell-to-module losses or unreasonable comparisons between hosts and cut cells. It is also demonstrated that application of the passivated edge technology (PET) yields I–V characteristics close to those of cells with ideal edges, i.e., without edge recombination. The implications on the module efficiency are also compared between modules built using cells with and without edge passivation, giving the highest efficiency for a shingled module with PET.