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  4. An 8 bit to 12 bit Resolution Programmable 5 MSample/s Current Steering Digital-to-Analog Converter in a 22 nm FD-SOI CMOS Technology
 
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2021
Conference Paper
Title

An 8 bit to 12 bit Resolution Programmable 5 MSample/s Current Steering Digital-to-Analog Converter in a 22 nm FD-SOI CMOS Technology

Abstract
We present a 5 MSample/s current steering digital-to-analog converter which has a programmable resolution between 8 bit, 10 bit and 12 bit. A selectable 2-D unary matrix architecture and a resolution programmable decoder are proposed for the resolution programmability. The proposed current steering digital-to-analog converter is implemented in a 22 nm FD-SOI (Fully Depleted Silicon-on-Insulator) CMOS technology. The simulation verifications of the CS-DAC at three resolution modes are made. The maximum DNL of 0.06 LSB is obtained at 8 bit resolution modes, and the maximum INL (Integral Non-Linearity) of 0.53 LSB is obtained at 12 bit resolution modes. The minimum SFDR (Spurious-Free Dynamic Range) of 47.93 dBc is obtained at 8 bit resolution mode.
Author(s)
Koh, Jeongwook  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Venkatesha, Shishira S.
Dresden University of Technology, Dresden, Germany
Rao, Sunil S.
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Jotschke, Marcel  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Lienig, Jens
Dresden University of Technology, Dresden, Germany
Reich, Torsten  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Mainwork
ICCSS 2021, 4th International Conference on Circuits, Systems and Simulation  
Project(s)
USeP
Funder
Sächsische Aufbaubank - Förderbank SAB  
Conference
International Conference on Circuits, Systems and Simulation (ICCSS) 2021  
DOI
10.1109/ICCSS51193.2021.9464215
File(s)
N-638342.pdf (938.38 KB)
Rights
Under Copyright
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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