Characterization of PVD Seed Layer Contact Resistance in 2.0 to 20.0 μ m Vias for Next-Generation WLP Interconnects

The versatility and scalability of wafer-level packaging are crucial aspects to meet the demand for higher I/O density. In WLP, interconnects are manufactured by sputter deposition of adhesion and seed layers followed by Cu electroplating. Spin-on organic materials are widely used as structural and insulating build-up layers. Prior PVD, it is common practice to pre-treat the wafer with degas and sputter etch. The goal of these steps is to desorb water and other volatile species, and to eliminate native oxide from the metal pads. The increased miniaturization and density of the interconnects, coupled with the presence of volatile contaminants released in the vacuum chambers, exponentially increase the challenge to control the contact resistance (Rc). In this work, we validated an improved process to fabricate Kelvin resistors used for the characterization of Rce at the interface between Al and Ti-Cu metallization. These two metal levels are separated by a PBO passivation that mimics the outgassing behavior of real WLP products. Several via diameters in the range of 20 μ m down to 2 μ m have been implemented in the mask-set in consideration of mature products, as well as next-generation developments. 300 mm Si wafers with different variations of Kelvin resistors are used as test vehicles to characterize PVD seed layer processes performed in a multi-chamber indexer system. The influence of via size on the Re performance is discussed and compared with RGA measurements recorded during the sputter etching process. The process-of-records executed at a steady-state throughput of 54.5 wafers/hour results in stable Rc on 20 and 10 μ m via structures. In contrast, a 20% Rc trend-up is observed on 3 and 2 μ m vias, indicating a higher sensitivity of these structures in regard to the accumulated chamber contamination. Measured RGA spectra confirm the build-up of volatile species occurring during continuous run. In conclusion, the fabricated Kelvin resistors represent reliable test vehicles that can be used to optimize wafer-to-wafer quality and improve yield in next-generation high-density interconnects.