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  4. The IC Ultra-Thin Back Surface - A Field of Real Nanoscale Fault Isolation Opportunities Requiring a Skillful Sample Preparation
 
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2022
Conference Paper
Title

The IC Ultra-Thin Back Surface - A Field of Real Nanoscale Fault Isolation Opportunities Requiring a Skillful Sample Preparation

Abstract
The backside approach of contactless fault isolation (CFI) was comfortable as long as it could be carried out with Near Infra-Red (NIR) optical techniques. But even with a solid immersion lens (SIL), the resolution was limited to ~180nm, corresponding to ca. 40nm node integrated circuit (IC) technologies. However, with failure analysis (FA) experience and circuit simulation, it was still successful down to 14 nm FinFET technology. There are several attempts to keep optical CFI competitive because the FA community has enormous experience to read and interpret the obtained signals. Two major strategies are out to save optical CFI for smaller nanoscale IC technologies: (1) shorter wavelength increases resolution by practically max. 2X, but then optical absorption is increasing by orders of magnitude so bulk silicon has to get very thin, and (2) sticking to NIR resolution and work with the signal mix coming from ca. 10 FETs inside the optical spot, requiring an increasing level of circuit and device knowledge involving big data and Artificial Intelligence/Machine Learning (AI/ML).Here, another way out will be presented: (3) fault isolation techniques with real nanoscale resolution like e-beam probing, backside nanoprobing and even near-field optical microscopy are possible if only the back surface of the IC is very close to the active device. This Ultra-Thin Silicon Back Surface (UTSBS) has already been explored to a certain extent. This work shows an overview about the results that are available and the still open field of opportunities. These techniques also support CFI in 3D systems. The sample preparation is very challenging as it has to get down very close to the device of interest but gives more degrees of freedom as only local planarity in a trench is required. No space for a SIL has to be created and the imaging or probing techniques have a long working distance.So, the ultra-thinning may be only necessary in local area, offering a number of preparation solutions consisting of mainly FIB trenching and laser etching. They can as well be composed of these techniques. It will also be presented how beneficial chemical mechanical polishing (CMP) can be.
Author(s)
Boit, Christian
Jatzkowski, Jörg
Fraunhofer-Institut für Mikrostruktur von Werkstoffen und Systemen IMWS  
Altmann, Frank  
Fraunhofer-Institut für Mikrostruktur von Werkstoffen und Systemen IMWS  
DiBattista, Michael
Silverman, Scott
Zwicker, Gerfried
Fraunhofer-Institut für Siliziumtechnologie ISIT  
Herfurth, Norbert
Amini, Elham
Seifert, Jean Pierre
Mainwork
IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2022  
Conference
International Symposium on the Physical and Failure Analysis of Integrated Circuits 2022  
DOI
10.1109/IPFA55383.2022.9915783
Language
English
Fraunhofer-Institut für Siliziumtechnologie ISIT  
Fraunhofer-Institut für Mikrostruktur von Werkstoffen und Systemen IMWS  
Keyword(s)
  • Chip Access through Backside

  • E-beam Probing

  • FIB backside trenching

  • IC Fault Isolation

  • Laser-assisted chemical Etching (LACE). Chemical-Mechanical Polishing (CMP)

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