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2012
Journal Article
Title
Significant on-resistance reduction of LDMOS devices by intermitted trench gates integration
Other Title
Wesentliche Verringerung des Driftwiderstands von LDMOS Bauelementen durch Einführung unterbrochener Grabenstrukturen
Wesentliche Verringerung des Ein-Widerstands in LDMOS Bauelementen durch Integration von Grabengates (lokal)
Abstract
A concept for the integration of intermitted trench gates into silicon lateral double-diffused metal-oxide-semiconductor (LDMOS) devices is proposed to achieve a significant reduction in on-resistance. The trench structure can be feasibly integrated into smart-power integrated circuit technology. Using 2-D technology computer aided design (TCAD) simulations, the achievable reduction in $R_{DS, {rm on}}$ from 145 $hbox{m}Omegacdot hbox{mm}{2}$ down to 94 $hbox{m}Omegacdothbox{mm}{2}$ for a 50 V LDMOS device and the negligible impact on the blocking characteristics were demonstrated. Additionally, the device parameters were analyzed with respect to static and dynamic power dissipation. Here, the benefits of trench gate integration became more apparent. Analyzing power losses during high-frequency operation revealed that the increased input capacitance resulting from the trench gate is acceptable for applications where high switching frequencies in the upper megahertz range are not required.
Open Access
File(s)
Rights
Under Copyright
Language
English
Keyword(s)
MOS integrated circuits
ICs
Power MOSFET
power semiconductor device
semiconductor device modeling
silicon devices
capacitance
integrated circuit
logic gates
power dissipation
standards
switches
topology
analyzing power
device parameters
high frequency operation
input capacitance
integrated circuit technology
LDMOS devices
metal oxide semiconductor
on-resistance
static and dynamic
technology computer aided design
trench gates