Impact of technological options for 22 nm SOI CMOS transistors on IC performance

Technological performance boost options for 22 nm fully depleted SOI transistor based CMOS circuits were studied by means of TCAD and SPICE simulations. The impact of two different rapid thermal annealing (RTA) schemes, including spike annealing and flash annealing, on IC performance was investigated using recently advanced models. Mechanical stress was used to improve the electrical performance of PMOS transistors. Parasitic interconnect capacitances of a state of the art low-k inter-metal dielectric and air-gap structures were extracted from topography simulations and used in SPICE simulations to observe the dynamic performance differences.