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2010
Report
Title
Self-checking arithmetic logic unit
Abstract
In this paper we present a new self-checking ALU with duplicated functional outputs. The arithmetic and logic functions as well as their inverses are implemented within a single ALU cell. Three new ALU cells which are intended for different application requirements (e.g. computational speed, hardware overhead and power consumption) are introduced. The hardware overhead for the implementation of the proposed ALU is lower than the hardware overhead required for complete duplication of the ALU and comparable with the hardware overhead required by the parity checked ALU. Thereby, the error detection capabilities are almost the same as for the complete duplication.
Publisher
Fraunhofer SIT
Publishing Place
Garching