Realization of transmission-gate conditional-sum -TGCCS- adders with low latency time

Transmission-gate conditional sum (TGCS) adders have been realized in a standard 2.5 Mym CMOS technology. These adders offer short propagation delay and latency time (12.5ns for 32-bit addition) and consume only moderate chip area (i.e. 80x460Mym2 for 1 bit in a 32-bit adder). The layout exhibits high regularity and can be easily adjusted to various word lengths. Design and layout techniques are described in detail and experimental data are given.