On the stability of fully depleted SOI MOSFETs under lithography process variations

In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of MOSFET devices has been evaluated by process and device simulations. FD SOI MOSFETs have been compared to bulk MOSFETs.