Efficient coding scheme for DDR4 memory subsystems

DRAMs face several major challenges: On the one hand, DRAM bit cells are leaky and must be refreshed periodically to ensure data integrity. Therefore, DRAM devices suffer from a large overhead due to refreshes both in terms of performance (available bandwidth) and power. On the other hand, reliability issues caused by technology shrinking are becoming a large concern. Thus, ECC techniques for DRAM errors, and especially for retention errors, gain more and more importance. In this paper, we present an investigation on DRAM errors and derive a detailed model for these types of errors. The model is verified by various measurements, and analyzed from an information theory point of view. Based on this model, a scheme is presented that largely improves DRAM's reliability with low overhead.