Crack and delamination risk evaluation in low-k BEoL stacks under chip package interaction aspects

The electronic industry drive for miniaturization and increasing functional integration forces the development of feature sizes down to the nanometer range. Moreover, harsh environmental conditions and new porous or nano-particle filled materials introduced on both chip and package level - low-k and ultra low-k materials in Back-end of line (BEoL) layers of advanced CMOS technologies, in particular - cause new challenges for reliability analysis and prediction. The authors show a combined numerical/experimental way and results towards optimized fracture resistance of those structures under chip package interaction aspects utilizing integral bulk and interface fracture concepts, VCCT and cohesive zone models in multi-scale and multi-failure modeling approaches with several kinds of imperfections. As important preconditions for high-quality simulations, nano-indentation AFM, FIB and EBSD provide the desired properties, while FIB-based trench techniques using deformation a nalyses by grayscale correlation and numerical simulations provide the intrinsic stresses especially of thin films in BEoL layers.