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  4. A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor
 
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2014
Conference Paper
Title

A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor

Abstract
In this paper, we propose a self-adaptive FPGA- based, partially reconfigurable system for space missions in order to mitigate Single Event Upsets in the FPGA configuration and fabric. Dynamic reconfiguration is used here for an on-demand replication of modules in dependence of current and changing radiation levels. More precisely, the idea is to trigger a redundancy scheme such as Dual Modular Redundancy or Triple Modular Redundancy in response to a continuously monitored Single Event Upset rate measured inside the on-chip memories itself, e.g., any subset (even used) internal Block RAMs. Depending on the current radiation level, the minimal number of replicas is determined at run- time under the constraint that a required Safety Integrity Level for a module is ensured and configured accordingly. For signal processing applications it is shown that this autonomous adaption to the different solar conditions realizes a resource efficient mitigation. In our case study, we show that it is possible to triplicate the data throughput at the Solar Maximum condition (no flares) compared to a Triple Modular Redundancy implementation of a single module. We also show the decreasing Probability of Failures Per Hour by 2 × 104 at flare-enhanced conditions compared with a non-redundant system. Our work is a part of the In-Orbit Verification of the Heinrich Hertz communication satellite.
Author(s)
Glein, Robért
Friedrich-Alexander-Universität Erlangen-Nürnberg, FAU
Schmidt, Bernhard
FAU
Rittner, Florian  
Teich, Jürgen
FAU
Ziener, Daniel
FAU
Mainwork
IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014. Proceedings  
Conference
International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2014  
DOI
10.1109/FCCM.2014.79
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Keyword(s)
  • VHDL

  • FPGA

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