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  4. Development of a low temperature SiC protection layer for post-CMOS MEMS fabrication utilizing vapour release technologies
 
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2016
Conference Paper
Title

Development of a low temperature SiC protection layer for post-CMOS MEMS fabrication utilizing vapour release technologies

Abstract
In post-CMOS processing a sufficient protection of the underlying CMOS structures, while applying sacrificial layer release technologies to realize free standing MEMS, is required. In this work, a low temperature Silicon Carbide (SiC) process at 300 C by Inductively Coupled Plasma Chemical Vapour Deposition (ICPCVD) has been developed. It has been demonstrated, that SiC provides an excellent protection character in HF=H2O vapour mixtures. For proof of principle, perforated free-standing SiC-structures with a layer thickness of less than 200 nm and 80 mm in diameter have successfully been released in a vapour etch process.
Author(s)
Walk, Christian  
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Chen, Yizhou
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Vidovic, Nino
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Kuhl, Andreas
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Görtz, Michael  
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Vogt, H.
Mainwork
Mikro-Nano-Integration. Beiträge des 6. GMM-Workshops 2016. CD-ROM  
Conference
Workshop Mikro-Nano-Integration 2016  
Language
English
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Keyword(s)
  • post-CMOS

  • MEMS

  • vapour HF

  • etching barrier

  • SiC

  • release etch

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