Study of the manufacture uncertainty impact of the hybrid SET-FET circuit
Abstract
Carry out an electronic device/circuit at the scale of few nanometers usually implies a high level of uncertainty due to device variability along the fabrication process. In fact, hybrid SET-FET circuit can be extremely delicate in front of parasitic elements, due to the low level of current provided by the SET device. So, in this contribution and study of their influence is done. Moreover, the suitability to implement this circuit by using FinFET SOI is observed, as well.
