Design process interactions in shallow trench isolation chemical mechanical planarization for layout diversification and design optimization

In this contribution we present an approach upon process window evaluation based on different STI test chip designs. General applicable process rules are derived, which help IC design engineers to care for key process requirements of CMP without full process insights. Special focus is laid on the sensitivity of the polish process result in structured areas on surrounding densities as well as the impact of large regions with homogenous density e.g. pure field regions. In a case study we will present the application of these general results derived from test chip experiments to a designers demand. The change of STI density was highly desirable from a device point of view, but limited by design rules. Such design rules are often very strict to ensure a safe fabrication, however for device diversification the existing rules might be too strict. To work with (exceptions from) such strict design rules a detailed process understanding is needed. Based on test chip experiments design scenarios to avoid device problems due to CMP process restrictions have been derived.