A method for characterizing the pad surface texture and modeling its impact on the planarization in CMP

Chemical-mechanical planarization (CMP) is one of the most demanding process steps in interconnect integration. Therefore, with respect to the pad roughness, we systematically characterize and model the planarization of special CMP test chips, which emulate integrated circuit (IC) layouts. Therefore, a novel pad roughness characterization methodology is developed and used for the extraction of important pad surface parameters like the mean asperities radius of curvature and the asperities size distribution. The obtained pad surface data is used for the derivation of a novel chip scale CMP model based on the Greenwood-Williamson theory. It is validated by experimental data from CMP test structures containing variations of both pattern-density and pattern-size and describes the wafer topology evolution with high accuracy throughout the planarization process, indicating a strong impact of the asperities size distribution on the planarization in test chip areas having trench widths smaller than the mean asperities radius of curvature.