PCB layout tool integrated loss and inductance estimation

This paper presents the implementation of the online inductance, loss and temperature distribution calculation integrated in a PCB layout tool. The parasitic inductances of certain current loops selected by the user are calculated with an existing PEEC solver. The developed add-on generates the 3D model automatically, activate the solver and extract the computation results. The loss solver implemented in the add-on calculates the losses and the temperature distribution according to a previously assigned current. As a result, the PCB layout designer is already efficiently supported during the design process. The method is validated using simulations and measurements of typical assemblies.