Precision analog circuit design in SOI CMOS for a wide temperature range up to 350°C

High resolution ADCs or voltage references require precision analog circuit design. However, design for a wide temperature range up to 350°C has been so far strongly impeded by a high dependency of the circuits' electrical properties, high leakage currents and severe performance losses. In this paper we present a body-biasing approach to reduce leakage currents and simultaneously improve the circuit's performance, i.e. intrinsic gain and bandwidth, and allow operation in the moderate inversion region of the transistor devices. The method presented here allows FD (fully depleted) device characteristics in a 1.0 µm PD (partially depleted) SOI (silicon-on-insulator) CMOS process. Results report a leakage current reduction of two orders of magnitude and a 200% improvement of the gm/Id factor in the moderate inversion region of the transistor.