CMOS-implementation of optimized 16-bit cordic-processors and evaluation tools

This paper is devoted to recursive CORDIC processors with 16 bit fixed-point arithmetics. After the presentation of unified and specialized CORDIC sequences which result from a parameter optimization of the algorithm, results of numerical experiments will be given which help to specify the internal data format and a proper rounding procedure. These algorithms are implemented on a CMOS CORDIC chip with a recursive architecture and a parameter RAM that allows programming with different CORDIC sequences. Evaluation tools for two parallel operating CORDIC processors will be presented. They include a development system as well as software tools like an assembler, a debugger, and self test programs.