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  4. Vertical 2T-nC FeRAM Demonstration: BEOL Read Transistor for 4F2 Memory Strings and Two-Terminal Selector Design for Polarization Disturb Mitigation
 
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2025
Conference Paper
Title

Vertical 2T-nC FeRAM Demonstration: BEOL Read Transistor for 4F2 Memory Strings and Two-Terminal Selector Design for Polarization Disturb Mitigation

Abstract
In this work, we demonstrate a vertical 2T-nC FeRAM with a back-end-of-line (BEOL) read transistor (T<inf>R</inf>) for 4 F<sup>2</sup> string and propose a selector design to mitigate polarization disturb in passive capacitor crossbar arrays. Key contributions include: 1) successful integration and operation composed of a Si MOSFET write transistor (T<inf>W</inf>), 3-layer cylindrical ferroelectric capacitors, and Si-doped In<inf>2</inf>O<inf>3</inf> BEOL T<inf>R</inf>, demonstrating the feasibility of 4 F<sup>2</sup> 2 T-nC string; 2) introducing nonlinearity into the capacitor stack to suppress ferroelectric voltage drop under inhibition biases while maintaining sufficient write voltage, reducing disturbance; 3)modeling and experimental validation of inserting a metalsemiconductor (a-Si)-metal (MSM) selector into the capacitor in mitigating the disturb, particularly achieving 9x reduction of disturb after 10<sup>6</sup> cycles in the V<inf>W</inf>/ 2 scheme.
Author(s)
Deng, Shan
University of Notre Dame
Howe, John
University of Notre Dame
Ma, Sizhe
University of Notre Dame
Tauki, Sadik Yasir
Pennsylvania State University
Zhao, Zijian
University of Notre Dame
Duan, Jiahui
University of Notre Dame
Lee, Yushan
University of Notre Dame
Qin, Yixin
University of Notre Dame
Joshi, Rajiv V.
IBM Thomas J. Watson Research Center
Kämpfe, Thomas  orcid-logo
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Gong, Xiao
National University of Singapore
Narayanan, Vijaykrishnan
Pennsylvania State University
Ni, Kai
University of Notre Dame
Mainwork
Digest of Technical Papers Symposium on VLSI Technology
Funder
U.S. Department of Energy
Conference
2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
DOI
10.23919/VLSITechnologyandCir65189.2025.11074964
Language
English
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
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