Entwurf eines FORTH-RISC Prozessors unter Einsatz von VERILOG-HDL und Logiksynthese Werkzeugen

This paper details the design flow of a 16-bit micro-controller using the Verilog Hardware description language and the SYNOPSYS logic synthesis tool. It describes the individual design steps from specification down to simulated netlist, the tools designed in a simplified architecture to verify our processor concept, using traditional design tools and 3mu m CMOS technology.