A codec chip architecture for (24, 12, 8) golay code with the permutation decoding
Abstract
An efficient ASIC chip of the Golay codec has been designed for channel coding. This paper describes the new architecture used in this chip and the ASIC design. Due to the new architecture which implements a permutation decoding algorithm based on a new minimum permuation set proposed by J. Wolfmann (A Permutation Decoding of the (24, 12,8) Golay code, IEEE Trans on Inform. Theory, vol. IT-29, no. 5, pp. 748-750, Sept. 1983), the codec architecture is relatively simple and a higher speed of the decoding procedure can be achieved compared with the Golay decoder of the decoding algorithms in common use, error-trapping algorithm and step-by-step method. From S-W. Wei and C-H. Wei (On High-Speed Decoding of the (23, 12,7) Golay Code, IEEE Trans. on Inform. Theory, vol IT-36, no. 3, pp. 692-695, May 1990) Kasami's error-trapping decoder requires 46 shift-operations for decoding one completely received word and the modified step-by-step decoder requires 35 shift-operations, while our decoder requires only 14 permutation operations, generalized shift operations. Consequently, this decoder can work faster than the Kasami's error-trapping decoder and the modified step-by-step decoder.
