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  4. Fabrication method for chip-scale-vacuum-packages based on a chip-to-wafer-process
 
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2010
Conference Paper
Title

Fabrication method for chip-scale-vacuum-packages based on a chip-to-wafer-process

Abstract
This paper introduces a simple vacuum packaging method which is based on a Chip-to-Wafer process. The MEMS-device is provided with an electroplated solder frame. A Si-lid with the same solder frame is mounted on each die of the wafer using a flip chip process. The same materials for lid and substrate are used in order to reduce the mechanical stress due to the same thermal coefficients of expansion. The resulting cavity between die and lid can be evacuated and hermetically sealed with an eutectic soldering process. The feasibility of the method is demonstrated with an infrared focal plane array (IR-FPA). In this case, the Si-lid acts as an optical window and contains an anti reflective layer for the 8-14 µm wavelength area on both sides. The long-term vacuum stability is supported by a getter film inside the package. This method simplifies the sawing process and has the additional cost benefit that it is possible to package only known good dies.
Author(s)
Bauer, Jochen
Weiler, Dirk  
Ruß, Marco
Heß, Jennifer  
Yang, Pin
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Voß, Jürgen
Arnold, Norbert
Vogt, Holger
Mainwork
Electro-optical and infrared systems: Technology and applications VII  
Conference
Electro-Optical and Infrared Systems - Technology and Applications Conference 2010  
DOI
10.1117/12.865019
Language
English
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
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