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Patent
Title
Verfahren zum Herstellen eines integrierten ionensensitiven Feldeffekttransistors in CMOS-Silizium-Planartechnologie
Other Title
Process for the production of an integrated ion-sensitive field effect transistor in CMOS silicon planar technology
Abstract
The present invention discloses a process for the production of an ion-sensitive field effect transistor that comprises the process steps of structuring a drain area, a source area and an ion-sensitive gate area, depositing a silicon dioxide/silicon nitrite double layer acting as a gate isolator, forming contact openings in the silicon dioxide/silicon nitrite double layer above the drain area and the source area, depositing and structuring conductors which contact the drain area and the source area directly, depositing an isolating surface planishing layer, etching a trench which extends up to the silicon dioxide/silicon nitrite double layer above the drain or source area adjacent to the ion-sensitive area, depositing a silicon carbide layer, and etching a recess surrounded by a trench, said recess extending up to the silicon dioxide/silicon nitrite double layer above the ion-sensitive area.
Inventor(s)
Hein, P.
Ramm, P.
Patent Number
1994-4430811
Publication Date
1995
Language
German