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  4. Interconnect challenges for CMOS technology. Materials, processes and reliability for downscaling, packaging and 3D stacking
 
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Title

Interconnect challenges for CMOS technology. Materials, processes and reliability for downscaling, packaging and 3D stacking

Title Supplement
April 9 - 13, 2012, San Francisco, California, USA; Symposium C, held at 2012 MRS spring meeting
Person Involved
Corporate Author
Materials Research Society -MRS-
Publisher
Cambridge University Press  
Publishing Place
Cambridge
Publication Date
2012
Series
Materials Research Society Symposium Proceedings; 1428
ISBN
978-1-6274-8237-0
Conference
Symposium C "Interconnect Challenges for CMOS Technology - Materials, Processes and Reliability for Downscaling, Packaging and 3D Stacking" 2012  
Materials Research Society (MRS Spring Meeting) 2012  
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