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  4. From Constraints to Tape-Out. Towards a Continuous AMS Design Flow
 
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2019
Conference Paper
Title

From Constraints to Tape-Out. Towards a Continuous AMS Design Flow

Abstract
The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve existing mixed-signal design flows:(1) automatic schematic generation from a system-level model,(2) flexible automatic analog layout generation, (3) constraint propagation and budget calculation for dependency resolution, and (4) verification of nonfunctional effects. The implementation of these steps results in a novel AMS design flow with a significantly higher degree of automation.
Author(s)
Krinke, Andreas
Technische Universität Dresden, Institute of Electromechanical and Electronic Design, Dresden, Germany
Horst, Tilman
Technische Universität Dresden, Institute of Electromechanical and Electronic Design, Dresden, Germany
Gläser, Georg
IMMS Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH Ilmenau, Germany
Grabmann, Martin
IMMS Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH Ilmenau, Germany
Markus, Tobias
Heidelberg University, ZITI, Computer Architecture Group, Heidelberg, Germany
Prautsch, Benjamin  orcid-logo
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Hatnik, Uwe  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Lienig, Jens
Technische Universität Dresden, Institute of Electromechanical and Electronic Design, Dresden, Germany
Mainwork
IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019  
Project(s)
Productive4.0
Funder
Bundesministerium für Bildung und Forschung BMBF (Deutschland)  
Conference
International Sympsoium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 2019  
Open Access
File(s)
Download (1.57 MB)
Rights
Use according to copyright law
DOI
10.1109/DDECS.2019.8724669
10.24406/publica-r-404550
Additional link
Full text
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Keyword(s)
  • IntelligentIP

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