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Direct growth of III–V/silicon triple-junction solar cells with 19.7% efficiency

: Feifel, Markus; Ohlmann, Jens; Benick, Jan; Hermle, Martin; Belz, Jürgen; Beyer, Andreas; Volz, Kerstin; Hannappel, Thomas; Bett, Andreas W.; Lackner, David; Dimroth, Frank

Postprint urn:nbn:de:0011-n-5280135 (731 KByte PDF)
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Created on: 10.1.2019

IEEE Journal of Photovoltaics 8 (2018), No.6, pp.1590-1595
ISSN: 2156-3381
ISSN: 2156-3403
Bundesministerium für Bildung und Forschung BMBF
10104-Grundlagenforschung Energie; 03SF0525A; MehrSi
Hocheffiziente III-V Mehrfachsolarzellen auf Silicium - 'Epitaxie, Prozessierung und Charakterisierung von III-V Mehrfachsolarzellen auf Silicium
Journal Article, Electronic Publication
Fraunhofer ISE ()
silicon; photovoltaic cell; gallium arsenide; lattice; substrates; Photovoltaik; Silicium-Photovoltaik; III-V und Konzentrator-Photovoltaik; Neuartige Photovoltaik-Technologien; Dotierung und Diffusion; III-V Epitaxie und Solarzellen; cells; arsenide

Monolithic multi-junction solar cells made on active silicon substrates are a promising pathway for low-cost high-efficiency devices. We present results of GaInP/GaAs/Si triple-junction solar cells, fabricated by direct growth on silicon in a metal-organic vapor phase epitaxy reactor using a GaAs y P 1-y buffer structure to overcome the lattice mismatch between Si and GaAs. A low-temperature (750 °C) Si surface preparation process and a SiN x diffusion barrier at the rear side have been implemented to maintain the minority carrier lifetime in the Si bottom cell. Conversion efficiencies up to 19.7% have been achieved under AM 1.5g spectral conditions. The cells are compared with identical GaInP/GaAs dual-junction solar cells grown on bulk GaP and GaAs substrates to identify loss mechanisms. Subcell electrical characterization using electroluminescence reveals a significant voltage loss of the III-V subcells on Si, compared with the same structures grown on GaP or GaAs. Electron channeling contrast imaging of the metamorphic GaAs y P 1-y buffer shows a three times higher threading dislocation density on Si (1.4 × 10 8 cm -2 ) than on GaP substrates, and atomic force microscopy shows holes in the GaAs y P 1-y buffer on Si that are not observed on GaP. Approaches to reach lower defect densities for the III-V layers on silicon are discussed.